The invention relates to a frequency synthesizer of the type which selects pulses from a clock pulse generator, of higher frequency (Fc) than the required output frequency (Fo), in order to provide said frequency Fo; the synthesizer including an adjustable accumulator of the type which, for each input clock pulse thereto, adds a preselected adjustable increment Y to the accumulated value in the accumulator and gives an output pulse each time an accumulated value C (where C is equal to or greater than Y) is reached or exceeded and leaves any excess as a residue in the accumulator.
In such frequency dividers, the required output frequency Fo is obtained, in effect, by the blanking out by the accumulator of some of the pulses from the clock pulse generator in order to produce the lower frequency Fo. However, the output pulses from the accumulator are synchronized to the clock pulses and are unevenly distributed with respect to time. The output pulse train therefore displays a considerable amount of phase jitter.
One method of at least substantially reducing the phase jitter is known from United Kingdom Patent Specification No. 1,447,418, in which the accumulator is incorporated in a phase lock loop comprising a phase comparator and a voltage-controlled variable frequency oscillator (VFO). The residue in the accumulator is converted to an analogue signal which is synchronized with, and balanced against, the output of the phase comparator to compensate for any variation in the output of the latter due to phase jitter in one of the input signals to the phase comparator. The required output frequency Fo is taken from the output of the VFO.